<html>
<head>
<link rel="shortcut icon" href="./favicon.ico">
<link rel="stylesheet" type="text/css" href="./style.css">
<link rel="canonical" href="./Pulse_Latch.html">
<meta name="viewport" content="width=device-width, initial-scale=1">
<meta name="description" content="Captures a high pulse and holds it until cleared.  This device simplifies FSM logic by converting a transient event into a steady signal that the FSM can pick up later once it reaches the correct state.">
<title>Pulse Latch</title>
</head>
<body>

<p class="inline bordered"><b><a href="./Pulse_Latch.v">Source</a></b></p>
<p class="inline bordered"><b><a href="./legal.html">License</a></b></p>
<p class="inline bordered"><b><a href="./index.html">Index</a></b></p>

<h1>Pulse Latch</h1>
<p>Captures a high pulse and holds it until cleared.  This device simplifies
 FSM logic by converting a transient event into a steady signal that the FSM
 can pick up later once it reaches the correct state.</p>

<pre>
`default_nettype none

module <a href="./Pulse_Latch.html">Pulse_Latch</a>
#(
    parameter RESET_VALUE = 1'b0
)
(
    input   wire    clock,
    input   wire    clear,
    input   wire    pulse_in,
    output  wire    level_out
);

    <a href="./Register.html">Register</a>
    #(
        .WORD_WIDTH     (1),
        .RESET_VALUE    (RESET_VALUE)
    )
    latch
    (
        .clock          (clock),
        .clock_enable   (pulse_in),
        .clear          (clear),
        .data_in        (1'b1),
        .data_out       (level_out)
    );

endmodule
</pre>

<hr>
<p><a href="./index.html">Back to FPGA Design Elements</a>
<center><a href="https://fpgacpu.ca/">fpgacpu.ca</a></center>
</body>
</html>

